AMD First to Launch FPGA Devices Featuring CXL 3.1 and PCIe Gen6

At Electronica, AMD introduced the Versal Premium Series Gen 2, the industry's first FPGA platform to support CXL 3.1 and PCIe Gen6.

AMD designed the Versal Premium Series Gen 2 for data centers, aerospace, communications, and test and measurement markets.

As AI and data analytics demands grow, the infrastructure supporting these technologies must keep up with the increasing data requirements. The rise of interconnected systems in data centers has heightened the importance of FPGAs in handling complex tasks. With advancements in memory scalability and security, AMD has positioned the scalable Versal Premium Series Gen 2 to meet the fast and secure data flow needs of industries that rely on stringent data movement.

All About Circuits spoke with Mike Rather, AMD's senior product line manager, to learn more about the new FPGA.

Advanced Interconnects

Rather described the Versal Premium Series Gen 2 as a “traffic manager” rather than a primary AI accelerator.

“We’re enabling AI, even though the GPU is the workhorse in this scenario,” he said. “Our role is to manage data movement quickly and efficiently so that GPUs can perform at peak levels.”

To this end, the Versal Premium Series Gen 2 employs advanced interconnect technology to handle high-speed, low-latency data movement between processors and accelerators in AI systems. It supports CXL 3.1 and PCIe Gen6, making it the first FPGA to integrate these latest industry standards.

 

Versal Premium Series Gen 2 Architecture

PCIe Gen6 provides 64 Gbps of bandwidth per lane, 2-4 times faster than previous generations. Meanwhile, CXL 3.1 enhances host-to-accelerator connectivity by offering memory coherency and pooling capabilities. CXL allows connected accelerators to share memory directly with the CPU, reducing redundant data transfers and latency. By combining PCIe Gen6 and CXL 3.1 support, AMD’s Versal Premium Series Gen 2 achieves a dual eight-lane interface, supporting up to 256 Gbps of aggregate bandwidth.

Memory Architecture

AMD also equipped the Versal Premium Series Gen 2 with an advanced memory architecture, including support for LPDDR5X memory at 8,533 Mbps and DDR5 memory at 6,400 Mbps. This configuration offers up to 2.7x the memory bandwidth compared to competitors still using DDR4 or LPDDR4 standards.

 

Expanding CXL in the Data Center

This FPGA can also integrate CXL-based memory expansion modules to further enhance its memory scalability. By supporting a multi-host, single-logic-device configuration, the Versal Premium Series Gen 2 can dynamically allocate and pool memory across multiple devices, a capability increasingly demanded by AI applications.

“With CXL memory expansion, we can augment LPDDR5X’s bandwidth by dynamically allocating memory pools across multiple devices,” Rather said. “This architecture supports a multi-headed single logic device (MH-SLD) without needing a switch, ultimately optimizing memory utilization.”

These features are critical for AI applications. CXL memory expansion reduces memory access latency, allowing AI cores to quickly access a larger memory pool. High-bandwidth interfaces allow accelerators to process and transmit data more efficiently. Additionally, AMD's FPGA devices include DSP engines that can perform mathematical operations required for AI, making them flexible enough to handle some inference tasks if needed.

Strengthened Security

For data security, the Versal Premium Series Gen 2 integrates a suite of features designed to protect data both in transit and at rest.

Crypto engine block diagram. 

It includes integrated PCIe integrity and data encryption (IDE) for secure data transmission, along with inline encryption for DDR memory for end-to-end protection across data flows. AMD also integrated two 400-Gbps high-speed crypto engines to accelerate encryption and decryption, doubling throughput over the previous generation. These engines support data protection at up to 800 Gbps, providing an added layer of security for real-time applications.

Timeline and Development Tools

AMD designed the Versal Premium Series Gen 2 for data centers, aerospace, communications, and test and measurement markets. Development tools for the Versal Premium Series Gen 2 are expected to be released in the second half of 2025, with silicon samples expected in early 2026 and production units by mid-2026.

“If you think about the entire AI era, data is like crude oil. The more data you have, the more you can do,” Rather concluded. “That’s what drives our need for memory and high-speed data transfer, pushing us to innovate on every level of connectivity and processing capability.”

Technology Discussion at Electronica 2024

All About Circuits Editor-in-Chief Jeff Child discussed the importance of the conference, AMD Xilinx FPGAs, and advances in industrial and vision applications with K.V. Bhaaskar, Senior Manager for Robotics at AMD.

All images courtesy of AMD.